`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    02:35:26 05/02/2013 
// Design Name: 
// Module Name:    Decoder 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Decoder(
	 input clk_50Mhz,
	 input reset_b,
    input pop_data,
    input [7:0] data_i,
    output reg [3:0] data_o,
    output reg [1:0] addr,
    output LDR,
    output sum,
    output cmp,
    output mul
    );
	 
 	
	 reg LDR_pulse_i;
	 reg sum_pulse_i;
	 reg cmp_pulse_i;
	 reg mul_pulse_i;
	 
	always @(posedge clk_50Mhz, negedge reset_b) begin

		if (reset_b == 1'b0) begin
		end
	
		else if ((pop_data ==1) && (data_i[1:0] == 2'b00)) begin
		
					LDR_pulse_i<=1;
					sum_pulse_i<=0;
					cmp_pulse_i<=0;
					mul_pulse_i<=0;
					
					data_o = data_i[7:4];
					addr = data_i[3:2];			
		end
		
		else if ((pop_data ==1) && (data_i[1:0] == 2'b01)) begin
		
					LDR_pulse_i<=0;
					sum_pulse_i<=1;
					cmp_pulse_i<=0;
					mul_pulse_i<=0;
					
					data_o = data_i[7:4];
					addr = data_i[3:2];			
		end
		
		else if ((pop_data ==1) && (data_i[1:0] == 2'b10)) begin
		
					LDR_pulse_i<=0;
					sum_pulse_i<=0;
					cmp_pulse_i<=0;
					mul_pulse_i<=1;
					
					data_o = data_i[7:4];
					addr = data_i[3:2];			
		end
		
		else if ((pop_data ==1) && (data_i[1:0] == 2'b11)) begin
		
					LDR_pulse_i<=0;
					sum_pulse_i<=0;
					cmp_pulse_i<=1;
					mul_pulse_i<=0;
					
					data_o = data_i[7:4];
					addr = data_i[3:2];			
		end
		else begin
					LDR_pulse_i<=0;
					sum_pulse_i<=0;
					cmp_pulse_i<=0;
					mul_pulse_i<=0;
		end			
			
	end
	
	PED LDR_pulse( .i_signal(LDR_pulse_i) , .i_clk(clk_50Mhz), .i_rst_b(reset_b), .o_pulse(LDR)); 
	PED sum_pulse( .i_signal(sum_pulse_i) , .i_clk(clk_50Mhz), .i_rst_b(reset_b), .o_pulse(sum)); 
	PED cmp_pulse( .i_signal(cmp_pulse_i) , .i_clk(clk_50Mhz), .i_rst_b(reset_b), .o_pulse(cmp)); 
	PED mul_pulse( .i_signal(mul_pulse_i) , .i_clk(clk_50Mhz), .i_rst_b(reset_b) ,.o_pulse(mul)); 


 endmodule

